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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADF4212L one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dual low power pll frequency synthesizer functional block diagram 12-bit if b-counter 6-bit if a-counter if prescaler output mux if lock detect charge pump rf lock detect charge pump 14-bit rf r-counter 14-bit if r-counter oscillator 22-bit data register sdout 12-bit rf b-counter 6-bit rf a-counter rf prescaler if phase frequency detector dgnd rf a gnd rf dgnd if a gnd if v dd 1 v dd 2 v p 1 v p 2 ADF4212L if in ref in clock data le rf in cp rf muxout cp if r set reference if current setting ifcp3 ifcp2 ifcp1 reference rfcp3 rfcp2 rfcp1 reference r set fl o fl o switch rf phase frequency detector features i dd total, 7.5 ma bandwidth rf/if, 2.4 ghz/1.0 ghz 2.7 v to 3.3 v power supply separate v p allows extended tuning voltage programmable dual modulus prescaler rf and if: 8/9, 16/17, 32/33, 64/65 programmable charge pump currents 3-wire serial interface analog and digital lock detect fastlock mode power-down mode 20-lead tssop and 20-lead mlf chip scale package applications wireless handsets (gsm, pcs, dcs, cdma, wcdma) base stations for wireless radio (gsm, pcs, dcs, cdma, wcdma) wireless lans cable tv tuners (catv) communications test equipment general description the ADF4212L is a dual frequency synthesizer that can be used to implement local oscillators (lo) in the up-conversion and down-conversion sections of wireless receivers and transmitters. it can provide the lo for both the rf and if sections. it con- sists of a low noise digital pfd (phase frequency detector), a precision charge pump, a programmable reference divider, pro- grammable a and b counters, and a dual modulus prescaler (p/ p + 1). the a (6-bit) and b (12-bit) counters, in conjunction with the dual modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14-bit reference counter (r counter), allows selectable refin frequencies at the pfd input. a complete pll (phase-locked loop) can be imple- mented if the synthesizer is used with external loop filters and vcos (voltage controlled oscillators). control of all the on-chip registers is via a simple 3-wire inter face with 1.8 v compatibility. the devices operate with a power supply ranging from 2.6 v to 3.3 v and can be powered down when not in use.
rev. 0 e2e ADF4212Lespecifications 1 (v dd 1 = v dd 2 = 2.7 v to 3.3 v; v p 1, v p 2 = v dd to 5.5 v; agnd rf = dgnd rf = agnd if = dgnd if = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 = ? = ? ? = ? = () ( + ) + = ====
rev. 0 e3e ADF4212L (v dd 1 = v dd 2 = 2.7 v to 3.3 v; v p 1, v p 2 = v dd to 5.5 v ; agnd rf = dgnd rf = agnd if = dgnd if = 0 v; t a = t min to t max , unless otherwise noted; dbm referred to 50 + ( ) ( =) = == === = == === = == === = == === () () () () ( ) ( = = = = = = = =
rev. 0 ADF4212L e4e caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADF4212L features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1, 2, 3 (t a = 25 ) + + + + + + + () + + ja thermal impedance . . . . . . . . . . . . . 150.4 ja thermal impedance (paddle soldered) . . . 122 ja thermal impedance (paddle not soldered) 216 () () === + + =() = ( )
rev. 0 ADF4212L e5e pin function description mnemonic description cp rf rf charge pump output. when enabled, this provides ? i r cp max set = r set = 2.7 k ? i cp max = 5 ma for both the rf and if charge pumps. agnd if ground pin for the if analog circuitry if in input to the if prescaler. this small signal input is normally ac-coupled from the if vco. cp if output from the if charge pump. this is normally connected to a loop filter that drives the input to an external vco. v p 2p ower supply for the if charge pump. this should be greater than or equal to v dd 2. in systems where v dd 2 is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range up to 5.5 v. v dd 2p ower supply for the if, digital, and interface section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. v dd 2 should have a value of between 2.6 v and 3.3 v. v dd 2 must have the same potential as v dd 1. v dd 1p ower supply for the rf section. decoupling capacitors to the ground plane should be placed as close as possible to this pin. v dd 1 should have a value of between 2.6 v and 3.3 v. v dd 1 must have the same potential as v dd 2. v p 1p ower supply for the rf charge pump. this should be greater than or equal to v dd 1. in systems where v dd 1 is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range up to 5.5 v.
rev. 0 ADF4212L e6e etypical performance characteristics amplitude e dbm 0 e5 e10 e15 e20 e25 e30 0 500 1000 1500 2000 frequency e mhz 2500 3000 v dd = 3 v v p = 5 v tpc 1. input sensitivity (rf input) amplitude e dbm 0 e5 e10 e15 e20 e25 e30 0 500 1000 1500 frequency e mhz e35 v dd = 3 v v p = 5 v tpc 2. input sensitivity (if input) output power e db 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 e2k e1k 1.75g 1k 2k frequency e hz reference level = e3.2dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds a verages = 22 e84.2dbc/hz tpc 3. phase noise, rf side (1750 mhz, 200 khz, 20 khz) output power e db 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 e400k e200k 1.75g 200k 400k reference level = e3.0dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 1hz video bandwidth = 1hz sweep = 2.5 seconds a verages = 20 e85.9db frequency e hz tpc 4. reference spurs, rf side (1750 mhz, 200 khz, 20 khz) phase noise e dbc/hz e50 e60 e70 e80 e90 e100 e110 e120 e130 e140 e150 100hz 1mhz frequency offset from 1.75ghz carrier 1.38 rms 10db/div rms noise = 1.38 degrees r l = e50dbc/hz tpc 5. integrated phase noise (1750 mhz, 200 khz/20 khz) output power e db 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 e2k e1k 540m 1k 2k reference level = e4.3dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds a verages = 22 e88.8dbc/hz frequency e hz tpc 6. phase noise, if side (540 mhz, 200 khz/20 khz)
rev. 0 ADF4212L e7e output power e db 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 e400k e200k 540m 200k 400k reference level = e7.0dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 1hz video bandwidth = 1hz sweep = 2.5 seconds a verages = 20 e89.3dbc frequency e hz tpc 7. reference spurs, if side (540 mhz, 200 khz, 20 khz) phase noise e dbc/hz e50 e60 e70 e80 e90 e100 e110 e120 e130 e140 e150 100hz 1mhz frequency offset from 540mhz carrier 0.83 rms 10db/div rms noise = 0.83 degrees r l = e50dbc/hz tpc 8. integrated phase noise (540 mhz, 200 khz/20 khz) phase detector frequency e khz 10 10000 phase noise e dbc/hz 1000 100 v dd = 3v v p = 5v e130 e140 e150 e160 e170 e180 tpc 9. phase noise referred to cp output vs. pfd frequency, rf side phase detector frequency e khz 10 10000 phase noise e dbc/hz 1000 100 v dd = 3v v p = 5v e130 e140 e150 e160 e170 e180 tpc 10. phase noise referred to cp output vs. pfd frequency, if side v cp e v 0 i cp e ma 1 6 4 2 0 e2 e4 2 3 4 5 e6 tpc 11. rf charge pump output characteristics v cp e v 0 i cp e ma 1 6 4 2 0 e2 e4 v dd = 3v v p 2 = 5.5v 2 3 4 5 e6 tpc 12. if charge pump output characteristics
rev. 0 ADF4212L e8e first reference spur e dbc/hz 0 e20 e40 e60 e80 e100 01 3 5 tuning voltage e v 2 4 tpc 13. rf reference spurs (200 khz) vs. v tune (1750 mhz, 200 khz, 20 khz) first reference spur e dbc 0 e20 e120 e40 e60 e80 e100 01234 tuning voltage e v 5 tpc 14. if reference spurs (200 khz) vs. v tune (1750 mhz, 200 khz, 20 khz) phase noise e dbc/hz 0 e10 e70 e20 e40 e50 e60 e40 e20 0 20 40 temperature e c 60 e80 e90 e100 e30 80 100 tpc 15. rf phase noise vs. temperature (1750 mhz, 200 khz, 20 khz) phase noise e dbc/hz 0 e10 e70 e20 e40 e50 e60 e40 e20 0 20 40 temperature e c 60 e80 e90 e100 e30 80 100 tpc 16. if phase noise vs. temperature (540 mhz, 200 khz, 20 khz) phase noise e dbc/hz 0 e10 e70 e20 e40 e50 e60 01234 tuning voltage e v 5 e80 e90 e100 e30 tpc 17. rf noise vs. v tune phase noise e dbc/hz 0 e10 e70 e20 e40 e50 e60 01234 tuning voltage e v 5 e80 e90 e100 e30 tpc 18. if noise vs. v tune
rev. 0 ADF4212L e9e first reference spur e dbc 0 e20 e40 e60 e40 e20 0 20 40 temperature e c 100 e80 e100 e120 60 80 tpc 19. rf spurs vs. temperature first reference spur e dbc 0 e20 e40 e60 e40 e20 0 20 40 temperature e c 100 e80 e100 e120 60 80 tpc 20. if spurs vs. temperature freq/ mhz 0.561872 0.529742 0.514244 0.405754 0.379354 0.312959 0.322646 0.288881 0.199294 0.206914 0.168344 0.092764 0.036125 0.037007 e0.053842 50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350 1450 s 11.real s11.imag s11.real s 11.imag e0.021077 e0.110459 e0.085802 e0.18583 e0.245482 e0.282399 e0.305457 e0.358884 e0.541032 e0.585687 e0.482539 e0.530108 e0.590526 e0.592498 e0.655932 0.97692 0.942115 0.961217 0.920667 0.897441 0.888164 0.850012 0.760189 0.767363 0.779511 0.761034 0.624825 0.635364 0.630242 0.634506 1550 1650 1750 1850 1950 2050 2150 2250 2350 2450 2550 2650 2750 2850 2950 e0.648879 e0.668172 e0.702192 e0.714541 e0.703593 e0.802878 e0.80397 e0.807055 e0.758619 e0.725029 e0.770837 e0.778619 e0.706197 e0.716939 e0.736527 freq/ mhz tpc 21. s parameter data for the rf input circuit description reference input section the reference input stage is shown in figure 2. sw1 and sw2 are normally-closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power-down. power-down control ref in nc nc no sw3 sw2 sw1 100k
rev. 0 ADF4212L e10e prescaler (p/p + 1) the dual-modulus prescaler (p/p + 1), along with the a and b counters, enables the large division ratio n, to be realized (n = pb + a). the dual-modulus prescaler, operating at cml levels, takes the clock from the rf/if input stage and divides it down to a manageable frequency for the cmos a and b counters in the rf and if sections. the prescaler in both sections is programmable. it can be set in software to 8/9, 16/17, 32/33, or 64/65. see table iv and table vi. it is based on a synchro nous 4/5 core. rf/if a and b counters the a and b cmos counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the pll feed- back counter. the counters are specified to work when the prescaler output is 200 mhz or less. typically, they will work with 250 mhz output from the prescaler. thus, with an rf input frequency of 2.5 ghz, a prescaler value of 16/17 is valid, but a value of 8/9 is not valid. pulse swallow function the a and b counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the equation for the vco frequency is as follows: fpbafr vco refin = () + [] f vco = output frequency of external voltage controlled oscillator (vco) p = preset modulus of dual modulus prescaler (8/9, 16/17, and so on) b = preset divide ratio of binary 13-bit counter (3 to 8191) a = preset divide ratio of binary 6-bit swallow counter (0 to 63) f refin =e xternal reference frequency oscillator r =p reset divide ratio of binary 14-bit programmable reference counter (1 to 16383) to pfd n = bp + a load load modulus control from rf input stage 12-bit b counter 6-bit a counter prescaler p/p+1 figure 4. rf/if a and b counters rf/if r counter the 14-bit rf/if r counter allows the input reference fre- quency to be divided down to produce the input clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 5 is a simplified schematic. the pfd includes a fixed delay element that sets the width of the antibacklash pulse. this is typically 3 ns. this pulse en sures that there is no dead zone in the pfd transfer function and gives a consistent reference spur level. d1 q1 clr1 u1 u3 delay hi up d2 q2 clr2 u2 down +in hi ein charge pump cp figure 5. rf/if pfd simplified schematic muxout and lock detect the output multiplexer on the ADF4212L allows the user to access various internal points on the chip. the state of mux- out is controlled by p3, p4, p11, and p12. see table iii and table v. figure 6 shows the muxout section in block dia- gram form. lock detect muxout can be programmed for two types of lock detect: d igital lock detect and analog lock detect. digital lock detect is active high. it is set high when the phase error on three con- secutive phase detector cycles is less than 15 ns. it will stay set high until a phase error of greater than 25 ns is detected on any subsequent pd cycle. the n-channel open-drain analog lock detect should be oper- ated with an external pull-up resistor of 10 k ?
rev. 0 ADF4212L e11e table i. c2, c1 truth table control bits c2 c1 data latch 00 if r counter 01 if n counter (a and b) 10 rf r counter 11 rf n counter (a and b) table ii. latch summary 15-bit reference counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (0) c2 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p2 p3 p4 if f o lock detect precision if r counter latch three-state cp if pd polarity p1 if cp current setting db23 ifcp2 db22 ifcp1 db21 ifcp0 r15 12-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (1) c2 (0) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b11 b12 p5 if n counter latch b10 if prescaler db23 p8 db22 p7 db21 p6 b9 if cp gain if power-down 6-bit a counter 15-bit rf reference counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (0) c2 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p10 p11 p12 rf f o rf lock detect rf r counter latch three-state cp rf pd polarity p9 rf cp current setting db23 rfcp2 db22 rfcp1 db21 rfcp0 r15 12-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (1) c2 (1) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b11 b12 p14 rf n counter latch b10 rf prescaler db23 p17 db22 p16 db21 p15 b9 rf cp gain rf power-down 6-bit a counter rf/if input shift register the ADF4212L digital section includes a 24-bit input shift register, a 14-bit if r counter, and an 18-bit if n counter (com- prising a 6-bit if a counter and a 12-bit if b counter). also present is a 14-bit rf r counter and an 18-bit rf n counter (comprising a 6-bit rf a counter and a 12-bit rf b counter). data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two c ontrol bits (c2, c1) in the shift register. these are the two lsbs, db1, and db0, as shown in the timing diagram of figure 1. the truth table for these bits is shown in table vi. table i shows a summary of how the latches are programmed.
rev. 0 ADF4212L e12e if r counter latch table iii. if r counter latch map 15-bit if reference counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (0) c2 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p2 p3 p4 if f o lock detect precision three-state cp if pd polarity p1 if cp current setting db23 ifcp2 db22 ifcp1 db21 ifcp0 r15 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 0 1 0 1 1 2 3 4 . . . 32764 32765 32766 32767 r15 r14 r13 .......... r3 r2 r1 divide ratio 0 1 negative positive p1 if pd polarity 0 1 output normal three-state p2 charge pump 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 logic low state if analog lock detect if reference divider output if n divider output rf analog lock detect rf/if analog lock detect if digital lock detect logic high state rf reference divider output rf n divider output three-state output if counter reset rf digital lock detect rf/if digital lock detect rf counter reset if and rf counter reset p12 p11 p4 p3 muxout from rf r latch 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 i cp (ma) 1.5k
rev. 0 ADF4212L e13e if n counter latch table iv. if n counter latch map 12-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (1) c2 (0) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b11 b12 p5 b10 if prescaler db23 p8 db22 p7 db21 p6 b9 if cp gain if power-down 6-bit a counter 0 0 . . . 1 1 1 1 0 0 . . . 1 1 1 1 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 1 . . . 1 1 1 1 1 0 . . . 0 0 1 1 1 0 . . . 0 1 0 1 3 4 . . . 4092 4093 4094 4095 b12 b11 b10 b3 b2 b1 b counter divide ratio 0 0 0 0 0 . . . 1 1 1 1 0 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 0 0 . . . 0 0 1 1 0 1 0 1 0 . . . 0 1 0 1 0 1 2 3 4 . . . 60 61 62 63 a6 a5 .......... a2 a1 a counter divide ratio 0 0 1 1 8/9 16/17 32/33 64/65 p6 prescaler value 0 1 0 1 p5 0 1 disabled enabled p7 if power-down 0 1 disabled enabled p8 if cp gain n = bp+a, p is prescaler value set in the function latch b must be greater than or equal to a for contiguous values of n, n min is (p 2 e p)
rev. 0 ADF4212L e14e rf r counter latch table v. rf r counter latch map 15-bit rf reference counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (0) c2 (1) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p10 p11 p12 rf f o rf lock detect three-state cp rf pd polarity p9 rf cp current setting db23 rfcp2 db22 rfcp1 db21 rfcp0 r15 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 1 1 1 1 0 1 1 0 . . . 0 0 1 1 1 0 1 0 . . . 0 1 0 1 1 2 3 4 . . . 32764 32765 32766 32767 r15 r14 r13 .......... r3 r2 r1 divide ratio 0 1 negative positive p9 rf pd polarity 0 1 normal three-state p10 rf charge pump output 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 logic low state if analog lock detect if reference divider output if n divider output rf analog lock detect rf/if analog lock detect if digital lock detect logic high state rf reference divider output rf n divider output three-state output if counter reset rf digital lock detect rf/if digital lock detect rf counter reset if and rf counter reset p12 p11 p4 p3 muxout from if r latch 0 0 0 0 1 1 1 1 rfcp2 0 0 1 1 0 0 1 1 rfcp1 0 1 0 1 0 1 0 1 rfcp0 i cp (ma) 1.5k
rev. 0 ADF4212L e15e rf n counter latch table vi. rf n counter latch map 12-bit b counter control bits db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 db10 db11 db12 db13 db14 db15 db16 db17 db18 db19 db20 c1 (1) c2 (1) a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 b7 b8 b11 b12 p14 b10 rf prescaler db23 p17 db22 p16 db21 p15 b9 rf cp gain rf power-down 6-bit a counter 0 0 1 1 8/9 16/17 32/33 64/65 p15 prescaler value 0 1 0 1 p14 0 1 disabled enabled p16 rf power-down 0 1 disabled enabled p17 rf cp gain n = bp+a, p is prescaler value set in the function latch b must be greater than or equal to a for contiguous values of n, n min is (p 2 e p) 0 0 0 0 0 . . . 1 1 1 1 0 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 0 0 . . . 0 0 1 1 0 1 0 1 0 . . . 0 1 0 1 0 1 2 3 4 . . . 60 61 62 63 a6 a5 .......... a2 a1 a counter divide ratio 0 0 . . . 1 1 1 1 0 0 . . . 1 1 1 1 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 1 . . . 1 1 1 1 1 0 . . . 0 0 1 1 1 0 . . . 0 1 0 1 3 4 . . . 4092 4093 4094 4095 b12 b11 b10 b3 b2 b1 b counter divide ratio
rev. 0 ADF4212L e16e program modes table iii and table v show how to set up the program modes in the ADF4212L. the following should be noted: 1. if and rf analog lock detect indicate when the pll is in lock. when the loop is locked and either if or rf analog lock detect is selected, then the muxout pin will show a logic high with narrow low going pulses. when the if/rf analog lock detect is chosen, then the locked condition is indicated only when both if and rf loops are locked. 2. the if counter reset mode resets the r and ab counters in the if section and also puts the if charge pump into three- state. the rf counter reset mode resets the r and ab counters in the rf section and also puts the rf charge pump into three-state. the if and rf counter reset mode does both of the above. upon removal of the reset bits, the ab counter resumes counting in close alignment with the r counter. (maximum error is one prescaler output cycle.) 3. the fastlock mode uses muxout to switch a second loop filter damping resistor to ground during fastlock operation. activation of fastlock occurs whenever rf cp gain in the rf reference counter is set to 1. if power-down it is possible to program the adf4210 family for either syn chro- nous or asynchronous power-down on either the if or rf side. synchronous if power-down programming a 1 to p7 of the ADF4212L will initiate a power- down. if p2 of the ADF4212L has been set to 0 (normal operation), a synchronous power-down is conducted. the de vice will automatically put the charge pump into three-state and com- plete the power-down. asynchronous if power-down if p2 of the ADF4212L has been set to 1 (three-state the if charge pump) and p7 is subsequently set to 1, an asynchro nous power-down is conducted. the device will go into power-down on the rising edge of le, which latches the 1 to the if power- down bit (p7). synchronous rf power-down programming a 1 to p16 of the ADF4212L will initiate a power-down. if p10 of the ADF4212L has been set to 0 (normal operation), a synchronous power-down is conducted. the device will automatically put the charge pump into three- state and then complete the power-down. asynchronous rf power-down if p10 of the ADF4212L has been set to 1 (three-state the rf charge pump) and p16 is subsequently set to 1, an asynchro nous power-down is conducted. the device will go into power-down on the rising edge of le, which latches the 1 to the rf power- down bit (p16). activation of either synchronous or asynchronous power-down forces the if/rf loop?s r and ab dividers to their load state conditions and the if/rf input section is debiased to a high impedance state. the ref in oscillator circuit is only disabled if both the if and rf power-downs are set. the input register and latches remain active and are capable of loading and latching data during all power-down modes. the if/rf section of the devices will return to normal powered-up operation immediately upon le latching a 0 to the appropriate power-down bit. if section programmable if reference (r) counter if control bits c2, c1 are 0, 0, the data is transferred from the input shift register to the 14-bit ifr counter. table iii shows the input shift register data format for the ifr counter and the divide ratios pos sible. if phase detector polarity p1 sets the if phase detector polarity. when the if vco char- acteristics are positive, this should be set to 1. when they are negative, it should be set to 0. see table iii. if charge pump three-state p2 puts the if charge pump into three-state mode when pro- grammed to a 1. it should be set to 0 for normal operation. see table iii. if program modes table iii and table v show how to set up the program modes in the ADF4212L. if charge pump currents ifcp2, ifcp1, ifcp0 program current setting for the if charge pump. see table iii. programmable if ab counter if control bits c2, c1 are 0, 1, the data in the input register is used to program the if ab counter. the n counter consists of a 6-bit swallow counter (a counter) and 12-bit programmable counter (b counter). table iv shows the input register data format for pro- gramming the if ab counter and the divide ratios possible. if prescaler value p5 and p6 in the if a, b counter latch set the if prescaler values. see table iv. if power-down table iii and table v show the power-down bits in the ADF4212L. if fastlock the if cp gain bit (p8) of the if n register in the ADF4212L is the fastlock enable bit. only when this is 1 is if fastlock enabled. when fastlock is enabled, the if cp current is set to maximum value. also an extra loop filter damping resistor to ground is switched in using the fl o pin, thus compensating for the change in loop characteristics while in fastlock. since the if cp gain bit is contained in the if n counter, only one write is needed to both program a new output frequency and ini tiate fast- lock. to come out of fastlock, the if cp gain bit on the if n register must be set to 0. see table iv.
rev. 0 ADF4212L e17e rf section programmable rf reference (r) counter if control bits c2, c1 are 1, 0, the data is transferred from the input shift register to the 14-bit rfr counter. table v shows the input shift register data format for the rfr counter and the divide ratios possible. rf phase detector polarity p9 sets the if phase detector polarity. when the rf vco charac- teristics are positive, this should be set to 1. when they are negative, it should be set to 0. see table v. rf charge pump three-state p10 puts the rf charge pump into three-state mode when pro- grammed to a 1. it should be set to 0 for normal operation. see table v. rf program modes table iii and table v show how to set up the program modes in the ADF4212L. rf charge pump currents rfcp2, rfcp1, rfcp0 program current setting for the rf charge pump. see table v. programmable rf n counter if control bits c2, c1 are 1, 1, the data in the input register is used to program the rf n (a + b) counter. the n counter consists of a 6-bit swallow counter (a counter) and 12-bit pro grammable counter (b counter). table iv shows the input register data format for programming the rf n counter and the divide ratios pos sible. see table vi. rf prescaler value p14 and p15 in the rf a, b counter latch set the rf prescaler values. see table vi. rf power-down table iii and table v show the power-down bits in the adf4210 family. rf fastlock the rf cp gain bit (p17) of the rf n register in the ad f4212l is the fastlock enable bit. only when this is 1 is if fastlock enabled. when fastlock is enabled, the rf cp current is set to maximum value. also, an extra loop filter damping resistor to ground is switched in using the fl o pin, thus compensating for the change in loop characteristics while in fastlock. since the rf cp gain bit is contained in the rf n counter, only one write is needed to both program a new output frequency and initiate fastlock. to come out of fastlock, the rf cp gain bit on the rf n register must be set to 0. see table vi. application section local oscillator for gsm handset receiver figure 7 shows the ADF4212L being used with a vco to produce the required los for a gsm base station transmitter or re ceiver. the reference input signal is applied to the circuit at fref in and, in this case, is terminated in 50 ? ? () (
rev. 0 ADF4212L e18e wideband pll many of the wireless applications for synthesizers and vcos in plls are narrow-band in nature. these applications include the various wireless standards like gsm, dsc1800, cdma, or wcdma. in each of these cases, the total tuning range for the local oscillator is less than 100 mhz. however, there are also wideband applications where the local oscillator could have up to an octave tuning range. for example, cable television tuners have a total range of about 400 mhz. figure 8 shows an appli- cation where the ADF4212L is used to control and program the micronetics m3500-1324. the loop filter was designed for an rf output of 2100 mhz, a loop bandwidth of 40 khz, a pfd frequency of 1 mhz, i cp of 10 ma (2.5 ma synthesizer i cp multiplied by the gain factor of 4), vco k d of 80 mhz/v (sen- sitivity of the m3500-1324 at an output of 2100 mhz) and a phase margin of 45 degrees. ref in dgnd rf a gnd rf dgnd if a gnd if rf in muxout r set v p 1v p 2 v dd 2 v dd 1 ADF4212L spi compatible serial bus clk data le 1000pf 1000pf 51
rev. 0 ADF4212L e19e interfacing the ADF4212L has a simple spi compatible serial interface for writing to the device. sclk, sdata, and le control the data transfer. when le (latch enable) goes high, the 22 bits that have been clocked into the input register on each rising edge of sclk will get transferred to the appropriate latch. see figure 1 for the timing diagram and table i for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 909 khz or one update every 1.1 = ( ) () ()
rev. 0 e20e c02774e0e11/02(0) printed in u.s.a. ADF4212L outline dimensions 20-lead thin shrink small outline package (tssop) (ru-20) dimensions shown in millimeters 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8

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